Verification engineers building for verification engineers
ChipAgents began in 2024 in San Jose, California
Coverage closure: chip verification's hardest unsolved problem
For ASIC teams shipping hardware, the final 15 percent of coverage costs the most. The holes may be roughly known, yet writing constrained-random tests by hand is slow and repetitive. That consumes the weeks before tape-out, when every other task is urgent too.
We started ChipAgents in 2024 to apply reasoning-capable language models to this coverage bottleneck. The aim is not to replace verification engineers, but to provide directed agents: describe the gap, review the result, run the test. Engineers retain judgment while agents take on authoring.
We are bootstrapped, early, and small. Our whole founding team works on the product daily. The early-access program runs structured five-day sprints with real ASIC teams, shaping every release.
Three values we follow
Depth over scale
Our sole focus is RTL verification, not a general coding agent or broad engineering assistant. Specialization earns the trust of engineers with deep domain expertise.
Engineer in loop
People review every agent output before integration. Sign-off is not automated. The verification engineer chooses what runs, while the agent prepares the draft.
RTL is yours
RTL and coverage data stay in memory during the active session only. We do not store or index them, or retain design files beyond their submitted sprint.
The team behind ChipAgents
William Wang
Co-founder, CEO
William Wang spent years leading functional verification for compute ASICs at a large semiconductor company, then joined an applied-AI startup before co-founding ChipAgents. He leads product direction and customer sprints.
Marcus Lin
Co-founder, CTO
Marcus Lin worked in EDA tooling and formal verification at a major EDA vendor, then researched machine learning in a university lab focused on program synthesis. He leads agent architecture and coverage analysis.
Lena Hoffmann
Head of Applications Engineering
Lena Hoffmann led verification infrastructure at a mid-size fabless chip company. She has deep expertise in UCDb integration, simulator compatibility, and regression pipeline design, and owns customer integration.
Partner on your next tape-out sprint
Early-access cohorts for ASIC and SoC design teams, kept small.
Request Access