ChipAgents Explained
Three agents aligned by your coverage database
Coverage-centered agent design
Each role is focused: Test Writer creates SystemVerilog, Coverage Tracker watches and ranks gaps, and Failure Explainer reasons back from assertion failures.
Test Writer: gap to SystemVerilog testbench
Provide Test Writer a coverage group and design block. It reads RTL, builds a constrained-random stimulus model, then produces a parameterized testbench for the gap. Engineers review and run it.
- Protocol-aware sequencers for constrained-random drivers
- Coverage group declarations match existing UCDb schema
- Engineers adapt the parameterized test structure quickly
- Human review before regression integration
Coverage Tracker: live gap ranking
Coverage Tracker parses your UCDb or UCIS database and ranks groups by urgency: structural gaps first, functional next, toggle last. This shows which 10 percent of effort yields the most coverage.
- Parses UCDb and UCIS from supported simulators
- Urgency scores put structural gaps above toggle misses
- Reanalyzes re-runs incrementally, no full re-import
- Coverage trends across regression runs
Failure Explainer: crash to RTL cause
After a simulation failure, Failure Explainer reads the wave dump, follows the assertion through the RTL hierarchy, and returns a structured triage note covering what failed, why, and which design signal to inspect.
- Reads VCD and FSDB via Cadence Xcelium and Synopsys VCS
- Follows assertion failures to signal origin in RTL hierarchy
- Distinguishes harness issues from genuine RTL bugs
- Structured triage note suggests the engineer's next step
No added simulator. Fits EDA flow.
ChipAgents links with your existing EDA toolchain via a lightweight API. Import a coverage database, export test vectors. Your simulator and EDA licenses stay the same.