Testbench writing repeats. Coverage review is manual. Failure triage takes days. The final 30 percent of coverage takes as much time as the first 70. Tape-out schedules slip here.
Three agents. One verification sprint.
01.
Test Writer
Reads RTL and builds SystemVerilog testbenches for uncovered branches. Includes constrained-random sequences, protocol-aware drivers, and coverage group declarations.
02.
Coverage Tracker
Tracks toggle, functional, and code coverage in real time, flagging emerging gaps. Highlights branches likely to conceal corner-case bugs before the regression window ends.
03.
Failure Explainer
Traces simulation failures to RTL root cause and returns a human-readable triage note. Cuts log-reading from hours to minutes.
Join your existing simulation flow in under an hour
1
Export your coverage database from Cadence Xcelium, Synopsys VCS, or QuestaSim. Use standard UCDb, with no simulator change.
2
ChipAgents agents analyze gaps and create targeted test vectors. The Test Writer makes SystemVerilog sequences; the Coverage Tracker shows which paths need attention.
3
Add generated tests to your regression then watch coverage close. Failures go to the Failure Explainer, which returns an actionable triage note.
Early-access pilots
Close coverage in days, not weeks
Three ASIC design teams in early access
~60%
Test authoring time versus manual testbench writing, measured in early-access sessions
3 hrs
Median time to the first coverage-gap report with an existing Cadence regression
We spent two weeks at 71 percent functional coverage before trying ChipAgents. The agents uncovered seven underspecified coverage groups and generated tests for each. Coverage closed in three days.
Senior Verification Engineer, fabless ASIC company, early-access program
The failure explainer exceeded my expectations. A clear English account of why a sim failed saves one hour of log-reading per failure. That adds up quickly in a big regression.
Lead RTL Engineer, compute chip design team, early-access program
Fits your EDA stack
Works with your current tools
ChipAgents reads coverage databases from Cadence Xcelium, Synopsys VCS, and QuestaSim. No new simulator or replacement.
Cadence Xcelium Synopsys VCS QuestaSim UCDb / UCIS SystemVerilog CI / CD Regression