Early-Access Program

Design teams close coverage faster

Early-access ASIC teams accelerated verification sprints with ChipAgents

Case Study

32-bit compute block: 71 to 96 percent in one sprint

A fabless ASIC team stood three weeks from tape-out with 71 percent functional coverage on a critical compute block. Its plan required 95 percent. In a five-day ChipAgents sprint, agents found 23 uncovered groups and created 41 targeted testbenches. Engineers reviewed and ran them, reaching 96 percent coverage by sprint end.

The team ran Cadence Xcelium and a standard UCDb database. ChipAgents integrated in under an hour. Test Writer created SystemVerilog testbenches for top-priority groups identified by Coverage Tracker. Failure Explainer supported resolution of two assertions found during the sprint.

Composite case study from the ChipAgents early-access pilot program. Company name withheld at request.

71 to 96% Critical compute block functional coverage

5 days Sprint time from UCDb import to target coverage

41 Targeted testbenches created by Test Writer

Pilot Data

Early-access pilot metrics

~3x

Earlier coverage gap identification than manual testplan review in early-access pilots

~60%

Less time authoring targeted testbenches across early-access sessions

<1 hr

Median time to integrate after the first coverage database import in pilot onboarding

In Their Words

Engineers report

Coverage Tracker prevented a late regression surprise by flagging a protocol-state gap two weeks before tape-out. Without ChipAgents, we would have found it during tape-out sign-off.

Principal Verification Engineer, SoC design group, early-access program

I initially doubted AI-generated testbenches. The first batch from the test writer contained one structural issue, while the rest ran clean. Iterating with the agent is faster than starting a review from scratch.

Verification Architect, mid-size chip company compute team, early-access program

ChipAgents joined our Xcelium flow in about 40 minutes. Their team guided us through the UCDb export, and coverage analysis was running that same afternoon.

Senior RTL Engineer, fabless design house, early-access program

Join a verification sprint cohort

Small cohorts of design teams enter structured early-access sprints.

Request Pilot Access