At 70 percent coverage, a regression for a real ASIC block often stops producing useful progress even though the simulator is still finding legal tests. In our work with small verification teams, the first 70 percent arrives during ordinary constrained-random runs, while the next 10 points can consume more time than the first 70 percent combined. That wall reflects the shape of the state space, not a lack of effort.
The Easy Side of the Curve
Early closure usually follows the behavior that a normal testbench already exercises. Nominal state-machine paths such as reset to idle, idle to active, and active to completion fill quickly. Data-path bins covering zero, maximum, and ordinary full-range values also tend to close in the first regression runs. Toggle coverage for most signals commonly completes in the same phase.
Common protocol traffic behaves similarly. An AXI read with a single beat and no back-pressure can cover many bins without a directed sequence. If the coverage groups describe the legal, expected flow, constrained-random stimulus reaches them with little bias.
The useful distinction is reachability without coordination. A bin belongs to the early portion when legal random inputs can reach it without arranging a particular history, timing relationship, or combination of independent conditions. The testbench runs, the database grows, and the coverage curve rises.
What Remains After 70 Percent
Above 70 percent, uncovered bins generally fall into two categories, and treating them alike wastes verification time.
Structurally hard bins are reachable, but only after several conditions occur together or in a precise order. Consider a memory interface whose read and write queues are full while error injection is enabled and back-pressure is asserted. A random generator may know that each condition is legal, yet almost never align all 4 conditions in one run. An error-recovery transition has the same problem when a new transaction arrives during a narrowly defined recovery state.
Misspecified bins look similar in a UCDB report, but the design or environment cannot reach them. The coverage group may describe behavior the RTL does not implement, or it may require an input combination that the testbench is forbidden to generate. Both categories appear as uncovered. Only reachability analysis separates them.
The Cost of an Optimistic Coverage Model
Coverage groups are often written while the testplan is still being refined, before the RTL behavior is fully settled. They encode design intent, then implementation details or legal stimulus constraints expose a mismatch. A bin can therefore remain open because the model is aspirational rather than because a test is missing.
We are not saying that an early coverage model was careless. We are saying that its assumptions need to be checked against the implemented state machine, protocol rules, and stimulus space. If the RTL structurally prevents a transition, the right action is a documented exclusion or waiver, not another week of stimulus development. The comment should explain why the bin is unreachable.
This review is expensive when done manually. A UCDB with 200 uncovered bins requires an engineer to inspect coverage definitions, trace RTL conditions, and compare them with legal constraints. The plan may allocate time for test writing but not for deciding which bins deserve a test at all. That unbudgeted classification work is a major part of the stall.
Why More Random Cycles Do Not Solve It
Constraint solvers are good at generating legal combinations. They are much less effective at navigating the temporal history needed to create a particular internal state. If a bin depends on three simultaneous conditions and each condition depends on the previous 20 clock cycles, the chance of reaching the target during a bounded simulation can be negligible.
That is a property of the state space, not a defect in the solver, simulator, or coverage database. Sparse corners require a path through the design, and the path usually has to be constructed deliberately. Running Xcelium, VCS, or QuestaSim for longer may increase total samples without materially increasing the probability of the required sequence.
A useful counter-point is that longer runs still matter when the bin is merely rare and has no deep dependency. The distinction is empirical. Check whether prior runs approach the necessary preconditions. If they do not, more cycles are unlikely to change the result.
A Practical Closure Sequence
For a team stalled at 70 percent, we start with classification, not new tests. Label every uncovered bin as structurally hard but reachable, misspecified and unreachable, or a genuine need for targeted stimulus. This separates model repair from sequence construction.
Misspecified bins are usually the fastest clean-up. Confirm the RTL behavior, legal input space, and coverage intent, then document justified exclusions. The coverage number can move without adding a test, while the remaining report becomes a more accurate work list.
For reachable gaps, create the preconditions explicitly. A targeted SystemVerilog test may fill queues, enable an error mode, hold a protocol phase, and then issue the transaction that exercises the bin. Its constraints should narrow the path instead of asking a general-purpose random test to discover it.
In early-access work with ChipAgents, the Coverage Tracker can read UCDB or UCIS-compatible results and group uncovered bins by structural clues. Timing-dependent protocol bins can be separated from state transitions with no path in the RTL graph. The Test Writer can then focus on bins that have a plausible closure path, while the Failure Explainer helps inspect why a proposed sequence still misses.
The exact mix varies by block. Protocol-heavy designs often leave more structurally hard bins. Designs with ambitious or early coverage models often leave more misspecified bins. Before adding simulation time, determine which kind of gap is present, because that decision determines whether the next action is a waiver, a directed sequence, or a coverage-model correction.